The present invention relates to insulated gate bipolar transistors, (hereinafter referred to as “IGBT's”) and diodes that constitute power semiconductor devices.
Power semiconductor devices have generally been used for non-contact switches. Therefore, it has been required for the power semiconductor devices to cause less losses therein. For reducing the losses caused therein, ON-state voltage lowering and switching loss reduction have been explored. It has been known to the persons skilled in the art that there exits a tradeoff relationship between the ON-state voltage and the switching (turnoff) loss of the power semiconductor devices. This tradeoff relationship is called the “ON-state-voltage turnoff-power-loss tradeoff relationship” for the IGBT's and the “forward-voltage reverse-recovery-loss tradeoff relationship” for the diodes.
These tradeoff relationships are the indices of loss generation in the power devices that have been required to be improved. The ON-state-voltage turnoff-power-loss tradeoff relationship and the soft switching performances are not simultaneously improved very often by the conventional methods known to persons skilled in the art. Therefore, it has been an important problem to improve both the ON-state-voltage turnoff-power-loss tradeoff relationship and the soft switching performances at the same time. Especially, since the turnoff-power-loss reduction is affected by the high-speed switching performances, it is important to improve the high-speed switching performances and the soft switching performances at the same time.
Recently, methods that control the excess carriers in the ON-state have been proposed for improving the ON-state-voltage turnoff-power-loss tradeoff characteristics of the IGBT's. For example, in the trench-type insulated gate bipolar transistor proposed in Japanese Unexamined Patent Application Publication No. 2000-228519, p-type well regions are formed selectively in the surface portion of an n-type drift layer such that the n-type drift layer has extended portions between the p-type well regions and the ratio Wt/Wp of the width Wt of the trench in the trench gate structure and the width Wp of the p-type well region is set at a value between 1 and 20.
Japanese Unexamined Patent Application Publication No. 2001-308327 proposes an insulated gate semiconductor device that includes a p-type base layer including a first region between a pair of trenches and a second region between an adjacent pair of trenches. The first region and n+-type source regions formed in the surface portions of the first region are in contact with an emitter electrode. The second region is not in contact with any emitter electrode. The ratio of the width of the first region to the width of the second region is set to be from 1:2 to 1:7.
Japanese Unexamined Patent Application Publication No. 2004-193212 proposes an improvement for semiconductor substrates which includes an n+-type buffer region and a first n−-type drift region in a drift region. The thickness of the first n−-type drift region and the impurity dose amount in the n+-type buffer region are determined so that the edge of the depletion layer expanding in the first n−-type drift region, when a rated voltage is applied, may stop in the n+-type buffer region. The semiconductor substrate further includes a second n−-type drift region spaced apart from first n−-type drift region for the n+-type buffer region. The thickness of the second n−-type drift region is set at a predetermined value.
Japanese Unexamined Patent Application Publication No. 2000-40822 proposes a super-junction semiconductor device including a semiconductor substrate region, that makes a current flow in the ON-state of the device and that is depleted in the OFF-state of the device. The semiconductor substrate region includes a plurality of vertical alignments of n-type buried regions and a plurality of vertical alignments of p-type buried regions. The vertical alignments of n-type buried regions and the vertical alignments of p-type buried regions are alternately arranged horizontally and periodically.
Japanese Unexamined Patent Application Publication No. 2006-294968 proposes a semiconductor device including a heavily doped n-type drain layer and an intermediate layer on the n-type drain layer. The intermediate layer is made of n-type Si and doped more lightly than the n-type drain layer. Through the intermediate layer, n-type layers made of n-type Si, doped more lightly than the drain layer and doped more heavily than the intermediate layer, are formed. The n-type layers work for a drift layer that provides a main current path when the device is operating. Further, p-type layers made of p-type Si are formed through the intermediate layer.
Japanese Unexamined Patent Application Publication No. Hei. 9 (1997)-232567 proposes a MOS-gate power device that includes a plurality of elementary functional units, each including a p-type body region formed in an n-type semiconductor material layer having a first resistivity value. Under each body region, a lightly doped n-type region having a second resistivity value higher than the first resistivity value is provided.
In the foregoing and following descriptions, electrons are majority carriers in the layer or the region with the prefix “n-type”. In the layer or the region with the prefix “p-type”, holes are majority carriers. The suffix “+” on the shoulder of the letter “n” or “p” indicating the conductivity type of the layer or the region indicates that the layer or the region is doped relatively heavily. The suffix “−” on the shoulder of the letter “n” or “p” indicating the conductivity type of the layer or the region indicates that the layer or the region is doped relatively lightly.
FIG. 20 is a cross sectional view showing the structure of a conventional trench-gate IGBT. As shown in FIG. 20, p-type channel layer 2 is formed in the surface portion on the side of the first major surface of lightly doped n-type main semiconductor layer 1. In the surface portion on the side of the second major surface of lightly doped n-type main semiconductor layer 1, heavily doped p-type collector layer 3 is formed. In n-type main semiconductor layer 1, uniformly doped n-type base layer 4 is disposed between p-type channel layer 2 and p-type collector layer 3. Between n-type base layer 4 and p-type collector layer 3, n+-type field stop layer 5 is disposed.
In the surface portion of p-type channel layer 2, n+-type emitter region 6 is formed selectively. In the surface portion of n-type main semiconductor layer 1 on the first major surface side, stripe-shaped trenches 7 are formed. Trench 7 is in contact with n+-type emitter region 6 and extended from the first major surface of n-type main semiconductor layer 1 to n-type base layer 4 through p-type channel layer 2. Gate electrode 9 is disposed in trench 7 with gate insulator film 8 interposed between gate electrode 9 and the inner wall of trench 7.
On the first major surface of n-type main semiconductor layer 1, interlayer insulator film 10 is disposed such that interlayer insulator film 10 covers gate electrode 9. On the first major surface of n-type main semiconductor layer 1, emitter electrode 11 formed of a metal film is disposed such that emitter electrode 11 is covering interlayer insulator film 10 and in contact with n+-type emitter region 6. In the surface portion of p-type channel layer 2, p+-type body region 12 is formed selectively. Emitter electrode 11 is connected electrically to p-type channel layer 2 via p+-type body region 12. Sometimes, a nitride film, an amorphous silicon film or a polyimide film is formed on emitter electrode 11 for a passivation film, although not illustrated in FIG. 20. Collector electrode 13 formed of a metal film is formed on p-type collector layer 3.
FIG. 21 is a cross sectional view showing the structure of a conventional planar-gate IGBT. As shown in FIG. 21, the impurity concentration distribution in n-type base layer 4 in the conventional planar-gate IGBT is uniform. In the surface portion on the side of the first major surface of n-type main semiconductor layer 1, p-type channel region 22 is formed selectively. In the surface portion of p-type channel region 22, n+-type emitter region 6 and p+-type body region 12 are formed selectively. Gate insulator film 8 is formed along the surface of p-type channel region 22 between n+-type emitter region 6 and n-type base layer 4. Gate electrode 9 is on gate insulator film 8. Gate electrode 9 is insulated from the regions in n-type main semiconductor layer 1 except p-type channel region 22 by the insulator film extending from gate insulator film 8. The other configurations are the same with those of the trench-gate IGBT shown in FIG. 20.
Now the operations of the IGBT while the IGBT is shifting form the OFF-state thereof to the ON-state thereof will be described below. As emitter electrode 11 is grounded and a voltage higher than the ground potential is applied to collector electrode 13 in the OFF-state of the IGBT, the IGBT is brought into an OFF-state under a voltage lower than the breakdown voltage due to the reversely biased junction between n-type base layer 4 and p-type channel layer 2 (p-type channel region 22). In this state, a voltage higher than the threshold voltage is applied from a not-shown gate driver circuit to gate electrode 9 via gate resistance. By the gate voltage application, electric charges start being accumulated on gate electrode 9. At the same time, an n-type channel region (not shown) reversed to the n-type is formed in the region of p-type channel layer 2 (p-type channel region 22) in contact with gate insulator film 8.
As the n-type channel region is formed between n+-type emitter region 6 and n-type base layer 4, the reversely biased junction vanishes from the path extending through the n-type channel region. Therefore, electrons are injected from emitter electrode 11 to n-type base layer 4 via n+-type emitter region 6 and the n-type channel region. Since the pn-junction on the collector side is biased in forward as the electron injection occurs, holes that are minority carriers are injected from p-type collector layer 3 to n-type base layer 4. As the holes are injected to n-type base layer 4, the concentration of the electrons that are majority carriers rises to maintain the neutral condition of the carriers in n-type base layer 4. As a result, the resistance of n-type base layer 4 is lowered. In short, the so-called conductivity modulation occurs. The voltage drop caused, when conductivity modulation occurs, by the current flowing between collector electrode 13 and emitter electrode 11 is the ON-state voltage.
Now the operations of the IGBT while the IGBT is shifting form the ON-state thereof to the OFF-state thereof will be described below. As the voltage between emitter electrode 11 and gate electrode 9 exceeds the threshold value to the lower side in the ON-state of the IGBT, the electric charges accumulated on gate electrode 9 are discharged to the gate driver circuit via the gate resistance. By the discharge, the channel region reversed to the n-type in p-type channel layer 2 (p-type channel region 22) returns to the p-type, making the channel region vanish. Therefore, the electron feed from emitter electrode 11 to n-type base layer 4 vanishes. However, a current keeps flowing until the electrons and holes accumulated in n-type base layer 4 are swept out to collector electrode 13 and emitter electrode 11 or recombine to vanish. After the electrons and holes in n-type base layer 4 vanish, the current does not flow and the IGBT is in the OFF-state thereof.
For realizing high-speed turnoff, it is necessary to increase the speed, at which the carriers accumulated in the n-type base layer are swept out at the turnoff, or the speed, at which the carriers accumulated in the n-type base layer recombine at the turnoff. However, as all the accumulated carriers are swept out by the space charge region while the voltage is rising or the current is decreasing in the early stage of turnoff, the current becomes 0 rapidly. Due to this, the left side of the following formula (1) describing the relation between the voltage and the current reduction rate becomes large rapidly and the collector voltage rises rapidly, causing hard switching. If hard switching is caused, voltage oscillation will be caused or over voltage breakdown will be caused. In the formula (1), V represents the voltage generated, Lc the wiring inductance, Ic the collector current and dlc/dt the time differentiation of the collector current.V=−Lc·dlc/dt  (1)
However, the conventional IGBT's described above have the problems as described below. In the semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 2004-193212, soft switching will be realized, if the accumulated charges are not swept out completely by the space charge region while the voltage is rising or the current is decreasing in the early stage of turnoff. However, it is difficult to realize high-speed turnoff, since the electrons and holes remaining in the neutral region decrease by diffusion or recombination. Since the semiconductor devices disclosed in Japanese Unexamined Patent Application Publication No. 2000-228519 and Japanese Unexamined Patent Application Publication No. 2001-308327 are subject to a size limitation and such a limitation on the emitter-side surface structure, it is necessary to design the semiconductor devices within the limitations. Since it is necessary for the semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. Hei. 9(1997)-232567 to form a lightly doped n-type region under a p-type region, design freedom is limited. It is necessary for the semiconductor devices disclosed in Japanese Unexamined Patent Application Publication No. 2000-40822 and Japanese Unexamined Patent Application Publication No. 2006-294968 to secure charge valance between the p-type semiconductor layer and the n-type semiconductor layer in the semiconductor substrate, but since pn-junctions exist in the semiconductor substrate in the semiconductor devices, input capacitance increase is caused and high-speed turnoff is prevented from occurring. If the second region of the p-type base layer not in contact with any n+-type source region is omitted from the semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 2001-30832, the breakdown voltage will be lowered greatly. If the p-type buried regions are omitted from semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 2000-40822, the breakdown voltage will be lowered greatly.
In view of the foregoing, it would be desirable to obviate the problems described above. It would be also desirable to provide a semiconductor device that facilitates realizing high-speed turnoff and soft switching at the same time.